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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document by MCM69F536C/D
32K x 36 Bit Flow-Through BurstRAM Synchronous Fast Static RAM
The MCM69F536C is a 1M-bit synchronous fast static RAM designed to provide a burstable, high performance, secondary cache for the 68K Family, PowerPCTM, 486, i960TM, and PentiumTM microprocessors. It is organized as 32K words of 36 bits each. This device integrates input registers, a 2-bit address counter, and high speed SRAM onto a single monolithic circuit for reduced parts count in cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K). BiCMOS circuitry reduces the overall power consumption of the integrated functions for greater reliability. Addresses (SA), data inputs (DQx), and all control signals except output enable (G) and Linear Burst Order (LBO) are clock (K) controlled through positive-edge-triggered noninverting registers. Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst addresses can be generated internally by the MCM69F536C (burst sequence operates in linear or interleaved mode dependent upon the state of LBO) and controlled by the burst address advance (ADV) input pin. Write cycles are internally self-timed and are initiated by the rising edge of the clock (K) input. This feature eliminates complex off-chip write pulse generation and provides increased timing flexibility for incoming signals. Synchronous byte write (SBx), synchronous global write (SGW), and synchronous write enable SW are provided to allow writes to either individual bytes or to all bytes. The four bytes are designated as "a", "b", "c", and "d". SBa controls DQa, SBb controls DQb, and so on. Individual bytes are written if the selected byte writes SBx are asserted with SW. All bytes are written if either SGW is asserted or if all SBx and SW are asserted. For read cycles, a flow-through SRAM allows output data to simply flow freely from the memory array. The MCM69F536C operates from a 3.3 V power supply and all inputs and outputs are LVTTL compatible. * MCM69F536C-7.5 = 7.5 ns Access / 12 ns Cycle MCM69F536C-8 = 8 ns Access / 12 ns Cycle MCM69F536C-8.5 = 8.5 ns Access / 12 ns Cycle MCM69F536C-9 = 9 ns Access / 12 ns Cycle MCM69F536C-10 = 10 ns Access / 15 ns Cycle MCM69F536C-12 = 12 ns Access / 16.6 ns Cycle * Single 3.3 V + 10%, - 5% Power Supply * ADSP, ADSC, and ADV Burst Control Pins * Selectable Burst Sequencing Order (Linear/Interleaved) * Internally Self-Timed Write Cycle * Byte Write and Global Write Control * 5 V Tolerant on all Pins (Inputs and I/Os) * 100-Pin TQFP Package
MCM69F536C
TQ PACKAGE TQFP CASE 983A-01
The PowerPC name is a trademark of IBM Corp., used under license therefrom. i960 and Pentium are trademarks of Intel Corp.
REV 5 3/23/99
(c) Motorola, Inc. 1999 MOTOROLA FAST SRAM
MCM69F536C 1
FUNCTIONAL BLOCK DIAGRAM
LBO ADV K ADSC ADSP K2
BURST COUNTER CLR 2
2
15 32K x 36 ARRAY
SA SA1 SA0
ADDRESS REGISTER
15
13
SGW SW WRITE REGISTER a
36
36
SBa
SBb
WRITE REGISTER b 4 WRITE REGISTER c DATA-IN REGISTER K
SBc
SBd
WRITE REGISTER d
K2
SE1 SE2 SE3 G
ENABLE REGISTER
DQa - DQd
MCM69F536C 2
MOTOROLA FAST SRAM
PIN ASSIGNMENT
SA SA SE1 SE2 SBd SBc SBb SBa SE3 VDD VSS K SGW SW G ADSC ADSP ADV SA SA DQc DQc DQc VDD VSS DQc DQc DQc DQc VSS VDD DQc DQc NC VDD NC VSS DQd DQd VDD VSS DQd DQd DQd DQd VSS VDD DQd DQd DQd 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 78 3 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 LBO SA SA SA SA SA1 SA0 NC NC VSS VDD NC NC SA SA SA SA SA NC NC
DQb DQb DQb VDD VSS DQb DQb DQb DQb VSS VDD DQb DQb VSS NC VDD NC DQa DQa VDD VSS DQa DQa DQa DQa VSS VDD DQa DQa DQa
MOTOROLA FAST SRAM
MCM69F536C 3
PIN DESCRIPTIONS
Pin Locations 85 84 Symbol ADSC ADSP Type Input Input Description Synchronous Address Status Controller: Initiates READ, WRITE, or chip deselect cycle. Synchronous Address Status Processor: Initiates READ, WRITE, or chip deselect cycle (exception -- chip deselect does not occur when ADSP is asserted and SE1 is high). Synchronous Address Advance: Increments address count in accordance with counter type selected (linear/interleaved). Synchronous Data I/O: "x" refers to the byte being read or written (byte a, b, c, d).
83 (a) 51, 52, 53, 56, 57, 58, 59, 62, 63 (b) 68, 69, 72, 73, 74, 75, 78, 79, 80 (c) 1, 2, 3, 6, 7, 8, 9, 12, 13 (d) 18, 19, 22, 23, 24, 25, 28, 29, 30 86
ADV DQx
Input I/O
G
Input
Asynchronous Output Enable Input: Low -- enables output buffers (DQx pins). High -- DQx pins are high impedance. Clock: This signal registers the address, data in, and all control signals except G and LBO. Linear Burst Order Input: This pin must remain in steady state (this signal not registered or latched). It must be tied high or low. Low -- linear burst count (68K/PowerPC). High -- interleaved burst count (486/i960/Pentium). Synchronous Address Inputs: These inputs are registered and must meet setup and hold times. Synchronous Address Inputs: These pins must be wired to the two LSBs of the address bus for proper burst operation. These inputs are registered and must meet setup and hold times. Synchronous Byte Write Inputs: "x" refers to the byte being written (byte a, b, c, d). SGW overrides SBx. Synchronous Chip Enable: Active low to enable chip. Negated high -- blocks ADSP or deselects chip when ADSC is asserted. Synchronous Chip Enable: Active high for depth expansion. Synchronous Chip Enable: Active low for depth expansion. Synchronous Global Write: This signal writes all bytes regardless of the status of the SBx and SW signals. If only byte write signals SBx are being used, tie this pin high. Synchronous Write: This signal writes only those bytes that have been selected using the byte write SBx pins. If only byte write signals SBx are being used, tie this pin low. Power Supply: 3.3 V + 10%, - 5%. Ground. No Connection: There is no connection to the chip. For compatibility reasons, it is recommended that this pin be tied low for system designs that do not have a sleep mode associated with the cache/memory controller. Other vendors' RAMs may have implemented this Sleep Mode (ZZ) feature. No Connection: There is no connection to the chip.
89 31
K LBO
Input Input
32, 33, 34, 35, 44, 45, 46, 47, 48, 81, 82, 99, 100 36, 37
SA SA1, SA0
Input Input
93, 94, 95, 96 (a) (b) (c) (d) 98
SBx SE1
Input Input
97 92 88
SE2 SE3 SGW
Input Input Input
87
SW
Input
4, 11, 15, 20, 27, 41, 54, 61, 65, 70, 77, 91 5, 10, 17, 21, 26, 40, 55, 60, 67, 71, 76, 90 64
VDD VSS NC
Supply Supply Input
14, 16, 38, 39, 42, 43, 49, 50, 66
NC
--
MCM69F536C 4
MOTOROLA FAST SRAM
TRUTH TABLE (See Notes 1 through 4)
Next Cycle Deselect Deselect Deselect Deselect Deselect Begin Read Begin Read Continue Read Continue Read Continue Read Continue Read Suspend Read Suspend Read Suspend Read Suspend Read Begin Write Begin Write Begin Write Continue Write Continue Write Suspend Write Suspend Write NOTES: 1. 2. 3. 4. Address Used None None None None None External External Next Next Next Next Current Current Current Current Current Current External Next Next Current Current SE1 1 0 0 X X 0 0 X X 1 1 X X 1 1 X 1 0 X 1 X 1 SE2 X X 0 X 0 1 1 X X X X X X X X X X 1 X X X X SE3 X 1 X 1 X 0 0 X X X X X X X X X X 0 X X X X ADSP X 0 0 1 1 0 1 1 1 X X 1 1 X X 1 X 1 1 X 1 X ADSC 0 X X 0 0 X 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 ADV X X X X X X X 0 0 0 0 1 1 1 1 1 1 X 0 0 1 1 G3 X X X X X 0 0 1 0 1 0 1 0 1 0 X X X X X X X DQx High-Z High-Z High-Z High-Z High-Z DQ DQ High-Z DQ High-Z DQ High-Z DQ High-Z DQ High-Z High-Z High-Z High-Z High-Z High-Z High-Z Write 2, 4 X X X X X READ READ READ READ READ READ READ READ READ READ WRITE WRITE WRITE WRITE WRITE WRITE WRITE
X = Don't Care. 1 = logic high. 0 = logic low. Write is defined as either 1) any SBx and SW low or 2) SGW is low. G is an asynchronous signal and is not sampled by the clock K. G drives the bus immediately (tGLQX) following G going low. On write cycles that follow read cycles, G must be negated prior to the start of the write cycle to ensure proper write data setup times. G must also remain negated at the completion of the write cycle to ensure proper write data hold times.
LINEAR BURST ADDRESS TABLE (LBO = VSS)
1st Address (External) X . . . X00 X . . . X01 X . . . X10 X . . . X11 2nd Address (Internal) X . . . X01 X . . . X10 X . . . X11 X . . . X00 3rd Address (Internal) X . . . X10 X . . . X11 X . . . X00 X . . . X01 4th Address (Internal) X . . . X11 X . . . X00 X . . . X01 X . . . X10
INTERLEAVED BURST ADDRESS TABLE (LBO = VDD)
1st Address (External) X . . . X00 X . . . X01 X . . . X10 X . . . X11 2nd Address (Internal) X . . . X01 X . . . X00 X . . . X11 X . . . X10 3rd Address (Internal) X . . . X10 X . . . X11 X . . . X00 X . . . X01 4th Address (Internal) X . . . X11 X . . . X10 X . . . X01 X . . . X00
WRITE TRUTH TABLE
Cycle Type Read Read Write Byte a Write Byte b Write Byte c Write Byte d Write All Bytes Write All Bytes SGW H H H H H H H L SW H L L L L L L X SBa X H L H H H L X SBb X H H L H H L X SBc X H H H L H L X SBd X H H H H L L X
MOTOROLA FAST SRAM
MCM69F536C 5
ABSOLUTE MAXIMUM RATINGS (See Note 1)
Rating Power Supply Voltage Voltage Relative to VSS for Any Pin Except VDD Output Current (per I/O) Package Power Dissipation (See Note 2) Temperature Under Bias Storage Temperature Symbol VDD Vin, Vout Iout PD Tbias Tstg Value - 0.5 to 4.6 - 0.5 to 6.0 20 1.6 - 10 to 85 - 55 to 125 Unit V V mA W C C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit.
NOTES: 1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPER- ATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. 2. Power dissipation capability is dependent upon package characteristics and use environment. See Package Thermal Characteristics.
PACKAGE THERMAL CHARACTERISTICS
Rating Thermal Resistance Junction to Ambient (@ 200 lfm) Thermal Resistance Junction to Board (Bottom) Thermal Resistance Junction to Case (Top) Single-Layer Board Four-Layer Board Symbol RJA RJB RJC Max 40 25 17 9 Unit C/W C/W C/W Notes 1, 2 1, 3 1, 4
NOTES: 1. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, board population, and board thermal resistance. 2. Per SEMI G38-87. 3. Indicates the average thermal resistance between the die and the printed circuit board. 4. Indicates the average thermal resistance between the die and the case top surface via the cold plate method (MIL SPEC-883 Method 1012.1).
MCM69F536C 6
MOTOROLA FAST SRAM
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V + 10%, - 5%, TA = 0 to 70C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS (Voltages Referenced to VSS = 0 V)
Parameter Supply Voltage Input Low Voltage Input High Voltage * VIL - 2 V for t tKHKH/2. ** VIH 6 V for tKHKH/2. Symbol VDD VIL VIH Min 3.135 - 0.5* 2.0 Typ 3.3 -- -- Max 3.6 0.8 5.5** Unit V V V
DC CHARACTERISTICS AND SUPPLY CURRENTS
Parameter Input Leakage Current (0 V Vin VDD) (Excluding LBO) Output Leakage Current (0 V Vin VDD) AC Supply Current (Device Selected, All Outputs Open, All Inputs Toggling at Vin VIL or VIH, Cycle Time tKHKH min) MCM69F536C-7.5 MCM69F536C-8 MCM69F536C-8.5 MCM69F536C-9 MCM69F536C-10 MCM69F536C-12 MCM69F536C-7.5 MCM69F536C-8 MCM69F536C-8.5 MCM69F536C-9 MCM69F536C-10 MCM69F536C-12 MCM69F536C-7.5 MCM69F536C-8 MCM69F536C-8.5 MCM69F536C-9 MCM69F536C-10 MCM69F536C-12 Symbol Ilkg(I) Ilkg(O) IDDA Min -- -- -- Max 1 1 320 320 320 320 310 300 150 150 150 150 140 130 55 55 55 55 50 45 0.4 -- Unit A A mA 1, 2, 3 Notes
CMOS Standby Supply Current (Deselected, Clock (K) Cycle Time tKHKH, All Inputs Toggling at CMOS Levels Vin VSS + 0.2 V or VDD - 0.2 V)
ISB1
--
mA
4
Clock Running Supply Current (Deselected, Clock (K) Cycle Time tKHKH,, All Other Inputs Held to Static CMOS Levels Vin VSS + 0.2 V or VDD - 0.2 V)
ISB2
--
mA
4
Output Low Voltage (IOL = 8 mA) Output High Voltage (IOH = - 4 mA) NOTES: 1. Reference AC Operating Conditions and Characteristics for input and timing. 2. All addresses transition simultaneously low (LSB) and then high (HSB). 3. Data states are all zero. 4. Device in deselected mode as defined by the Truth Table.
VOL VOH
-- 2.4
V V
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25C, Periodically Sampled Rather Than 100% Tested)
Parameter Input Capacitance Input/Output Capacitance Symbol Cin CI/O Min -- -- Typ 4 7 Max 6 9 Unit pF pF
MOTOROLA FAST SRAM
MCM69F536C 7
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V + 10%, - 5%, TA = 0 to 70C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . 1 V/ns (20% to 80%) Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . . . See Figure 1 Unless Otherwise Noted
READ/WRITE CYCLE TIMING (See Notes 1, 2, and 3)
-7.5 Parameter P Cycle Time Clock High Pulse Width Clock Low Pulse Width Clock Access Time Output Enable to Output Valid Clock High to Output Active Clock High to Output Change Output Enable to Output Active Output Disable to Q High-Z Clock High to Q High-Z Setup Times: Address ADSP, ADSC, ADV Data In Write Chip Enable Hold Times: Address ADSP, ADSC, ADV Data In Write Chip Enable Symbol S bl tKHKH tKHKL tKLKH tKHQV tGLQV tKHQX1 tKHQX2 tGLQX tGHQZ tKHQZ Min 12 4 4 -- -- 0 3 0 -- 2.5 2.5 tADKH tADSKH tDVKH tWVKH tEVKH 0.5 tKHAX tKHADSX tKHDX tKHWX tKHEX -- 0.5 -- 0.5 -- 0.5 -- 0.5 -- 0.5 -- ns Max -- -- -- 7.5 5 -- -- -- 5 5 -- Min 12 4 4 -- -- 0 3 0 -- 2.5 2.5 -8 Max -- -- -- 8 5 -- -- -- 5 5 -- -8.5 Min 12 4 4 -- -- 0 3 0 -- 2.5 2.5 Max -- -- -- 8.5 5 -- -- -- 5 5 -- Min 12 4 4 -- -- 0 3 0 -- 3 2.5 -9 Max -- -- -- 9 5 -- -- -- 5 5 -- -10 Min 15 5 5 -- -- 0 3 0 -- 3 2.5 Max -- -- -- 10 5 -- -- -- 5 5 -- -12 Min 16.6 6 6 -- -- 0 3 0 -- 3 2.5 Max -- -- -- 12 6 -- -- -- 6 6 -- Unit Ui ns ns ns ns ns ns ns ns ns ns ns 4 4 4 4, 5 4, 5 Notes N
NOTES: 1. Write is defined as either any SBx and SW low or SGW is low. Chip Enable is defined as SE1 low, SE2 high, and SE3 low whenever ADSP or ADSC is asserted. 2. All read and write cycle timings are referenced from K or G. 3. G is a don't care after write cycle begins. To prevent bus contention, G should be negated prior to start of write cycle. 4. This parameter is sampled and not 100% tested. 5. Measured at 200 mV from steady state.
OUTPUT Z0 = 50 RL = 50 VT = 1.5 V
Figure 1. AC Test Load
MCM69F536C 8
MOTOROLA FAST SRAM
READ/WRITE CYCLES
tKHKL tKLKH
tKHKH
K
MOTOROLA FAST SRAM
B C D tKHQV BURST WRAPS AROUND tGLQV Q(A) tKHQX1 tKHQX2 Q(B) Q(B+1) Q(B+2) Q(B+3) tGHQZ Q(B) D(C) ADSP, SA SE2, SE3 IGNORED BURST READ BURST WRITE D(C+1) D(C+2) D(C+3) tGLQX Q(D) SINGLE READ
SA
A
ADSP
ADSC
ADV
SE1
E
W
G
DQx
Q(n)
tKHQZ
DESELECTED
SINGLE READ
MCM69F536C 9
NOTE: E low = SE2 high and SE3 low. W low = SGW low and/or SW and SBx low.
APPLICATION INFORMATION
The MCM69F536C BurstRAM is a high speed synchronous SRAM that is intended for use primarily in secondary or level two (L2) cache memory applications. L2 caches are found in a variety of classes of computers -- from the desktop personal computer to the high-end servers and transaction processing machines. For simplicity, the majority of L2 caches today are direct mapped and are single bank implementations. These caches tend to be designed for bus speeds in the range of 33 to 66 MHz. At these bus rates, flow-through (non-pipelined) BurstRAMs can be used since their access times meet the speed requirements for a minimum-latency, zero-wait state L2 cache interface. Latency is a measure (time) of "dead" time the memory system exhibits as a result of a memory request. For those applications that demand bus operation at greater than 66 MHz or multi-bank L2 caches at 66 MHz, the pipelined (register/register) version of the 32K x 36 BurstRAM (MCM69P536) allows the designer to maintain zero-wait state operation. Multiple banks of BurstRAMs create additional bus loading and can cause the system to otherwise miss its timing requirements. The access time (clock-to- valid-data) of a pipelined BurstRAM is inherently faster than a non-pipelined device by a few nanoseconds. This does not come without cost. The cost is latency -- "dead" time. For L2 cache designs that must minimize both latency and wait states, flow-through BurstRAMs are the best choice in achieving the highest performance in L2 cache design. NON-BURST SYNCHRONOUS OPERATION Although this BurstRAM has been designed for 68K-, PowerPC-, 486-, i960-, and Pentium-based systems, these SRAMs can be used in other high speed L2 cache or memory applications that do not require the burst address feature. Most L2 caches designed with a synchronous interface can make use of the MCM69F536C. The burst counter feature of the BurstRAM can be disabled, and the SRAM can be configured to act upon a continuous stream of addresses. See Figure 2. CONTROL PIN TIE VALUES EXAMPLE (H VIH, L VIL)
Non-Burst Sync Non-Burst, Flow-Through SRAM ADSP H ADSC L ADV H SE1 L SE2 H LBO X
NOTE: Although X is specified in the table as a don't care, the pin must be tied either high or low.
K
ADDR
A
B
C
D
E
F
G
H
SE3
W
G
DQ
Q(A)
Q(B)
Q(C)
Q(D)
D(E)
D(F)
D(G)
D(H)
READS
WRITES
Figure 2. Example Configuration as Non-Burst Synchronous SRAM
MCM69F536C 10
MOTOROLA FAST SRAM
ORDERING INFORMATION
(Order by Full Part Number) MCM
Motorola Memory Prefix Part Number
69F536C XX
XX X
Blank = Trays, R = Tape and Reel Speed (7.5 = 7.5 ns, 8 = 8 ns, 8.5 = 8.5 ns, 9 = 9 ns, 10 = 10 ns, 12 = 12 ns) Package (TQ = TQFP)
Full Part Numbers -- MCM69F536CTQ7.5 MCM69F536CTQ8 MCM69F536CTQ8.5 MCM69F536CTQ9 MCM69F536CTQ10 MCM69F536CTQ12
MCM69F536CTQ7.5R MCM69F536CTQ8R MCM69F536CTQ8.5R MCM69F536CTQ9R MCM69F536CTQ10R MCM69F536CTQ12R
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
MOTOROLA FAST SRAM
MCM69F536C 11
PACKAGE DIMENSIONS
TQ PACKAGE TQFP CASE 983A-01
4X
e e/2
0.20 (0.008) H A-B D
2X 30 TIPS
0.20 (0.008) C A-B D -D-
80 81 51 50
B E/2 B VIEW Y E1 E E1/2
BASE METAL PLATING
-X- X=A, B, OR D
-A-
-B-
b1 c
100 1 30
31
D1/2 D1 D
2X 20 TIPS
D/2
0.13 (0.005)
0.20 (0.008) C A-B D
A -H- -C-
SEATING PLANE
q
2
0.10 (0.004) C
q
3 VIEW AB
0.05 (0.002)
S
S
q
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -A-, -B- AND -D- TO BE DETERMINED AT DATUM PLANE -H-. 5. DIMENSIONS D AND E TO BE DETERMINED AT SEATING PLANE -C-. 6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS D1 AND B1 DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 7. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE b DIMENSION TO EXCEED 0.45 (0.018). DIM A A1 A2 b b1 c c1 D D1 E E1 e L L1 L2 S R1 R2
q q q q
1 0.25 (0.010)
GAGE PLANE
A2
R2
A1
R1
L2 L L1 VIEW AB
q
1 2 3
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MCM69F536C 12
EEEE CCCC EEEE CCCC
b
M MILLIMETERS MIN MAX --- 1.60 0.05 0.15 1.35 1.45 0.22 0.38 0.22 0.33 0.09 0.20 0.09 0.16 22.00 BSC 20.00 BSC 16.00 BSC 14.00 BSC 0.65 BSC 0.45 0.75 1.00 REF 0.50 REF 0.20 --- 0.08 --- 0.08 0.20 0_ 7_ 0_ --- 11 _ 13 _ 11 _ 13 _
c1
C A-B
S
D
S
SECTION B-B
INCHES MIN MAX --- 0.063 0.002 0.006 0.053 0.057 0.009 0.015 0.009 0.013 0.004 0.008 0.004 0.006 0.866 BSC 0.787 BSC 0.630 BSC 0.551 BSC 0.026 BSC 0.018 0.030 0.039 REF 0.020 REF 0.008 --- 0.003 --- 0.003 0.008 0_ 7_ 0_ --- 11 _ 13 _ 11 _ 13 _
Mfax is a trademark of Motorola, Inc.
MOTOROLAMCM69F536C/D FAST SRAM

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